The invention relates to a multi-phase MOS integrated circuit comprising a plurality of groups of combinatory logic elements for forming an associated AND/OR/INVERSION function in each group, at least one data connection of each group of combinatory logic elements being coupled to a data connection of at least one of the other groups, said integrated circuit comprising clock inputs for receiving the signals of a multi-phase clock-pulse cycle having a plurality of clock pulses, at least one clock pulse per cycle controlling a sample operation. An integrated circuit of this kind is known from previous Netherlands Patent Application No. 7809397 (corresponding to U.S. Pat. No. 4,371,795). The known circuit is an example of dynamic MOS logic, which is typified by the fact that no direct current can occur between the power terminals. For the design of very large scale integrated circuits (VLSI), an optimum compromise is sought for three characteristic variables, that is to say power dissipation, the delay time required for a given logic operation, and the surface area required for given function; all these variables should be as low as possible. All known technologies have their specific relative drawbacks.
Herein, combinatory logic elements are to be understood to mean elements in which a transition of an input signal causes a signal transition on the output or not, regardless of the instant of occurrence of the former transition. In sequential logic elements of separation exists between input and output: when a signal transition on the input occurs prior to a given instant, this signal transition can influence the output signal. If the signal transition on the input occurs later, the output signal will remain the same at least for the time being. Herein an AND/OR/INVERSION function is to be understood to mean a function which comprises an arbitrary combination of AND-functions and OR-functions, followed by an inherent inversion. Herein a data connection is to be understood to mean a data input as well as a data output. In the cited dynamic MOS technology, the logic operations are performed in a succession of clock cycles. Upon the transition between two successive clock cycles the resultant signals are temporarily stored in hold circuits. This offers the logic designer a high degree of freedom, but also results in a comparatively slow circuit because the number of logic levels or logic depth of the function which can be formed per clock cycle is limited.